Laterally diffused (LD) transistors, such as laterally diffused metal-oxide-semiconductor (LDMOS) transistors, are widely employed in high voltage applications, including power management applications. To provide flexibility in terminal connections and shielding the impact from surrounding devices, isolation is needed. Conventional techniques to isolate LDMOS employ two deep isolation wells of opposite polarity type. For example, in the case of a n-type LDMOS, an additional deep p-type isolation well is employed in addition to the deep n-type isolation well. The additional p-type isolation well is shallower than the deep n-type isolation well. The use of two deep isolation wells requires an additional mask, undesirably increasing cost. Furthermore, the additional p-type isolation well is restricted by the depth of the n-type isolation well.
In addition, conventional LDMOS transistors have deep drift regions to improve drain voltage endurance. However, deep drift regions restrict channel dimension shrinkage, as well as increasing junction capacitance due to the high dopant dosage required. This negatively impacts scalability and performance.
The present disclosure is directed to a scalable LDMOS with low junction capacitance to improve performance.